1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a synchronous delay circuit system including a synchronous delay circuit formed in a semiconductor integrated circuit and having a function of controlling a delay time of the clock signal.
2. Description of Related Art
In the prior art, a synchronous delay circuit, capable of removing a clock skew for a short time, is used in a high speed synchronous circuit, from the viewpoint of a simple circuit construction and a small current consumption. Examples of the prior art synchronous delay circuit are disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-08-237091 (corresponding to European Patent Application Pre-examination Publication No. EP-0 720 291-A2), Toshio Yamada et al, "Capacitance coupled Bus with Negative Delay Circuit for High Speed and Low Power (10 GB/s&lt;500 mW) Synchronous DRAMs", 1996 Symp. on VLSI Circ. pp. 112-113, Jim-Man Han et al, "Skew Minimization Technique for 256M-bit Synchronous DRAM and beyond", 1996 Symp. on VLSI Circ. pp 192-193, Richard B. Watson et al, "Clock Buffer Chip with Absolute Delay Regulation Over Process and Environment Variations", Proc. of IEEE 1992 CICC (Custom Integrated Circuits Conference) 25.2, and Yoshinori OKAJIMA et al, "Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Inteface", IEICE TRANS. ELECTRON., VOL. E79-C, NO. 6, JUNE 1996 pp. 798-807. The content of these documents is incorporated by reference in their entirety into this application.
FIG. 7 is a circuit diagram illustrating a basic construction of the synchronous delay circuit system in accordance with the first prior art example. This synchronous delay circuit system includes an input buffer 3 having a first delay time td1 and receiving an external clock CLK1 having a clock period tCK, a clock driver 4 having a second delay time td2 and outputting an internal clock CLK2, a dummy delay circuit 5 having a delay time td1+td2 corresponding to the sum of the first and second delay times td1 and td2 of the input buffer 3 and the clock driver 4, a first delay circuit array 1 formed of a predetermined number of delay circuits having a predetermined delay time, for measuring a time difference of a constant period from an output of the dummy delay circuit 5, and a second delay circuit array 2 formed of a predetermined number of delay circuits having a predetermined delay time, for reproducing the measured time difference to output the reproduced time difference to the clock driver 4.
Here, the dummy delay circuit 5 includes an input buffer dummy 5a which is completely the same as the input buffer 3, and a clock driver dummy 5b which is completely the same as the clock driver 4, in order to make the delay circuit arrays 1 and 3 equal to the delay times td1 and td2 of the input buffer 3 and the clock driver 4.
Each of the delay circuit arrays 1 and 2 is formed of a predetermined number of delay circuits having a predetermined equal delay time. The constant period of time is measured by the delay circuit array 1, and is reproduced by the delay circuit array 2. This function is realized by causing a signal to progress in the delay circuit array 1 during a period of time by be measured, and to causing a signal to pass in the delay circuit array 2 through delay circuits of the same number as that of the delay circuits through which the first named signal has progressed.
A system in which a signal is caused to pass in the delay circuit array 2 through the delay circuit of the same number as that of the delay circuits through which a signal has progressed in the delay circuit array 1, can be classified into two types based on whether an end of the path or the whole of the path are selected for determining the length of the delay circuit array 2. The synchronous delay circuit system applied with these methods is also divided into two, on the basis of the signal progressing directions of the delay circuit arrays, and therefore, the system can be classified into four types.
Namely, if the system is classified on the basis of the signal progressing directions of the delay circuit arrays 1 and 3, it is classified into one in which, as shown in FIG. 8 (prior art 2) and FIG. 9 (prior art 3), the respective signal progressing directions of the delay circuit arrays 1 and 2 are opposite to each other, and the number of delay circuits in the delay circuit arrays 2 is determined by an input terminal side of the delay circuit array 2, and another in which, as shown in FIG. 10, (prior art 4) and FIG. 11 (prior art 5), the respective signal progressing directions of the delay circuit array 1 and 2 are equal to each other, and the number of delay circuits in the delay circuit arrays 2 is determined by an output terminal side of the delay circuit array 2.
By classifying in this manner, the examples shown in FIG. 8 (prior art 2) and FIG. 11 (prior art 5) correspond to the example of selecting the end of the path, and the examples shown in FIG. 9 (prior art 3) and FIG. 10 (prior art 4) correspond to the example of selecting the whole of the path. Incidentally, in the example shown in FIG. 10 (prior art 4), a control circuit array 6 formed of control gates of the number corresponding to the number of the delay circuits in each of the delay circuit arrays 1 and 2 is located between the delay circuit arrays 1 and 2, and a multiplexor (MUX) 7 is located at an output side of the delay circuit array 2.
For reference, the example shown in FIG. 8 corresponds to one disclosed in JP-A-08-237091 (corresponding to EP-0 720 291-A2), and the example shown in FIG. 9 corresponds to one disclosed in Yoshinori OKAJIMA et al, "Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface", IEICE TRANS. ELECTRON., VOL. E79-C, NO. 6, JUNE 1996 pp. 798-807. The example shown in FIG. 10 corresponds to one disclosed in Jim-Man Han et al, "Skew Minimization Technique for 256M-bit Synchronous DRAM and beyond", 1996 Symp. on VLSI Circ. pp. 192-193, and the example shown in FIG. 11 corresponds to one disclosed in Toshio Yamada et al, "Capacitance coupled Bus with Negative Delay Circuit for High Speed and Low Power (10 GB/s&lt;500 mW) Synchronous DRAMs", 1996 Symp. on VLSI Circ. pp. 112-113.
In the above mentioned synchronous delay circuit systems, since the traveling speed of a pulse or a signal edge is a constant in the two delay circuit arrays (first delay circuit array and second delay circuit array), if the synchronous delay circuit system is used in a low frequency, the pulse or the signal edge overflows from the first delay circuit array depending upon the period of the external clock, so the synchronous delay circuit system does not operate normally.
This problem can be overcome by elongating each of the first delay circuit array beforehand, and the second delay circuit array so they have a large delay time. However, the number of delay circuits required to from each of the first delay circuit array and the second delay circuit array becomes large, so that the area occupied by the delay circuit array also becomes large, and therefore, the overall circuit scale becomes large.